The core of a semiconductor memory comprises at least one two-dimensional memory cell array, where information is stored. Traditionally, word-lines select rows, which activate cells, and bit-lines select columns, which access, i.e., read or write, the cells. When a word-line and a bit line are activated, a particular memory cell connected to them is selected.
To activate a word-line, its voltage is normally set to a high voltage (Vdd), which is equal to a positive supply voltage in a CMOS circuitry. Setting a word-line to a low voltage (Vss), which is a voltage complimentary to the positive supply voltage, deactivates the word-line. While the low voltage is customarily set to ground, or 0 V, the value for the high voltage can be different for various semiconductor manufacturing technologies. For instance, in a deep-submicron technology, a high voltage can be 1.2 V or even lower, while in a submicron technology the high voltage can be 2.5 V. But for a given memory chip and a given technology, the high voltage is normally designed to a fixed value, and this is particularly true for a complimentary-metal-oxide-semiconductor (CMOS) memory circuitry. DVS (dynamic voltage scaling) is often used to reduce power consumption. However, only small VDD scaling ranges can be used for memory circuits when compared with surrounding digital logic circuitry. For this reason, memory circuits are often operated at the higher VDD, or a dual-rail design is applied.
Since there are multiple memory cells connected to a single word-line, and the word-line itself can be very long depending on the memory array size and technology used, so the word-line can be quite a load for its corresponding decoder, then a driver is needed to drive the word-line. The word-line driver couples, on one end, to a word-line decoder output, and on the other end, to a word-line. When a memory chip is in an active mode, i.e., the memory chip is ready for being actively read or written, the word-line driver functions just as a regular driver, following the word-line decoder, and providing a current source to pull up the word-line to a high voltage when the word-line is selected, and pull down the word-line to a low voltage when the word-line is not selected. When the memory chip is in a standby mode, i.e., the memory cannot be actively read or written, and the power consumption is maintained at a minimum just to retain the information stored in the memory cell arrays, then the word-line driver clamps the word-line voltage to low.
Semiconductor Random Access Memory (RAM) circuits store logic states by applying either a high voltage level (such as for logic “1”) or a low voltage level (such as for logic “0”) to the memory cell transistors that comprise the memory array. In word line voltage control circuits, the high and low (or negative) voltage levels are applied to a selected word line in a selected sector of the memory array by a decoder circuit. Current word line drivers typically used in SRAM (static RAM) devices are NAND-style decoders that are followed by one or more stages of inverters to buffer the signal. This design is generally optimal for active power and performance, but results in high power consumption due to leakage power losses. In certain operation modes, this leakage power can dominate the active power consumption of the memory chip.
Conventional power gating schemes for word-line drivers in SRAM arrays utilizes a segment-based or macro-based approach (hereinafter referred to as “blocks” or “block-based”). Each block includes a plurality of word lines, such as 1024 lines. The word-line drivers are powered on by block control signal and not powered down unless the block is disabled in its entirety. This block-based approach is inefficient in terms of both metal routing and power consumption.
FIG. 1 is a circuit diagram of a prior art word-line driver circuit 10 for use in this type of memory cell. The word-line driver includes a NAND circuit 12, which includes transistors M1, M2 and M3, an output inverter 14, which includes transistors M4 and M5, and a power gating device 16 shown as transistor M6. The NAND circuit 12 and inverter circuit 14 cooperate to provide an AND function, with address signals XDEC and WLPY as inputs to the AND gate. As those familiar with these types of word-line drivers will understand, XDEC and wlpy are bus signals for a block of, for example, 1024 word-lines, which can be expressed as xdec[*] and wlpy[*]. For a single word-line driver circuit, there are only one XDEC and one wlpy signals. Both XDEC and wlpy are address signals. XDEC is the output of a word-line decoder circuit and wlpy is the product of an address signal passed through a clock gating circuit to be form a pulse signal.
Assuming block select signal PD is of the proper bias to turn power gating transistor M6 “on” then the driver circuit 10 operates such that when both signal XDEC, and signal WLPY are high (meaning WLPY bar (WLPYB) is low), the output signal WL is logical high (“1”). Otherwise, the output signal WL is logical low (“0”). As can be seen from FIG. 1, the word-line driver circuit 10 is designed in the high-Vdd (Vddh) domain, while surrounding peripherals may be designed in the low-Vdd (Vddl) domain for dual rail power schemes. This approach requires a level shifter circuit (not shown) to provide control signal PD. This peripheral circuit lowers the power efficiency of the memory array. Moreover, power gating device M6 is often centralized in the array to serve several word line drivers. This layout consumes a lot of metal routing resources.
An improved word-line driver circuit is desired.